[I]
Digital I/O
Digital Input (Make / NO)
A Normally Open (NO) interactive switch or a receiver for an output with the same tag.
Inputs (0)
—
Outputs (1)
Q
TYPE: INPUTWire in Lab
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[I (NC)]
Digital I/O
Digital Input (Break / NC)
A Normally Closed (NC) break contact. It outputs true when the switch is NOT pressed.
Inputs (0)
—
Outputs (1)
Q
TYPE: NC_INPUTWire in Lab
[KEY]
Digital I/O
Cursor key
Planned keyboard direction input for interactive control panels.
Inputs (0)
—
Outputs (1)
Q
TYPE: CURSOR_KEYWire in Lab
[F-KEY]
Digital I/O
Text display function key
Planned function key for a simulated text display; no physical display connection.
Inputs (0)
—
Outputs (1)
Q
TYPE: TD_FUNCTION_KEYWire in Lab
[BIT]
Digital I/O
Shift register bit
Planned reader for one bit in a named shift register.
Inputs (0)
—
Outputs (1)
Q
TYPE: SHIFT_REGISTER_BITWire in Lab
[1]
Digital I/O
Status 1 (high)
A constant true signal.
Inputs (0)
—
Outputs (1)
Q
TYPE: HIGHWire in Lab
[0]
Digital I/O
Status 0 (low)
A constant false signal.
Inputs (0)
—
Outputs (1)
Q
TYPE: LOWWire in Lab
[Q]
Digital I/O
Digital output
An output indicator that also publishes its state to matching input tags.
Inputs (1)
A
Outputs (1)
Q
TYPE: OUTPUTWire in Lab
[X]
Digital I/O
Open connector
Planned explicit termination for an intentionally unused digital signal.
Inputs (1)
A
Outputs (0)
—
TYPE: OPEN_CONNECTORWire in Lab
[M]
Digital I/O
Digital flag
A named digital signal marker that can publish to matching input tags.
Inputs (1)
A
Outputs (1)
Q
TYPE: FLAGWire in Lab
[AI]
Analog I/O
Analog input
An adjustable numeric input or receiver for an analog output with the same tag.
Inputs (0)
—
Outputs (1)
Q
TYPE: ANALOG_INPUTWire in Lab
[AQ]
Analog I/O
Analog output
A numeric output display that publishes to matching analog input tags.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_OUTPUTWire in Lab
[AM]
Analog I/O
Analog flag
A named numeric signal marker that can publish to matching analog input tags.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_FLAGWire in Lab
[#]
Analog I/O
Analog constant
A configurable numeric reference for setpoints and calculations.
Inputs (0)
—
Outputs (1)
Q
TYPE: ANALOG_CONSTANTWire in Lab
[NI]
Network
Network input
Planned digital input from a named simulation channel; hardware adapters are separate work.
Inputs (0)
—
Outputs (1)
Q
TYPE: NETWORK_INPUTPlanned Phase 4
[NAI]
Network
Network analog input
Planned numeric input from a named simulation channel.
Inputs (0)
—
Outputs (1)
Q
TYPE: NETWORK_ANALOG_INPUTPlanned Phase 4
[NQ]
Network
Network output
Planned digital publication to a simulation channel.
Inputs (1)
A
Outputs (1)
Q
TYPE: NETWORK_OUTPUTPlanned Phase 4
[NAQ]
Network
Network analog output
Planned numeric publication to a simulation channel.
Inputs (1)
A
Outputs (1)
Q
TYPE: NETWORK_ANALOG_OUTPUTPlanned Phase 4
[&]
Logic
AND
True when both inputs are true.
Inputs (2)
AB
Outputs (1)
Q
TYPE: ANDWire in Lab
[&↑]
Logic
AND (edge)
Planned one-scan pulse when the AND result becomes true.
Inputs (2)
AB
Outputs (1)
Q
TYPE: AND_EDGEWire in Lab
[!&]
Logic
NAND
False when both inputs are true.
Inputs (2)
AB
Outputs (1)
Q
TYPE: NANDWire in Lab
[!&↑]
Logic
NAND (edge)
Planned one-scan pulse when the NAND result becomes true.
Inputs (2)
AB
Outputs (1)
Q
TYPE: NAND_EDGEWire in Lab
[≥1]
Logic
OR
True when either input is true.
Inputs (2)
AB
Outputs (1)
Q
TYPE: ORWire in Lab
[!≥1]
Logic
NOR
True when neither input is true.
Inputs (2)
AB
Outputs (1)
Q
TYPE: NORWire in Lab
[=1]
Logic
XOR
True when exactly one input is true.
Inputs (2)
AB
Outputs (1)
Q
TYPE: XORWire in Lab
[=]
Logic
XNOR
True when both inputs have the same state.
Inputs (2)
AB
Outputs (1)
Q
TYPE: XNORWire in Lab
[!]
Logic
NOT
Inverts a digital signal.
Inputs (1)
A
Outputs (1)
Q
TYPE: NOTWire in Lab
[TON]
Timers
On-delay
Turns on after A remains true for the duration; resets when A becomes false.
Inputs (1)
A
Outputs (2)
QET
TYPE: TONWire in Lab
[TOF]
Timers
Off-delay
Turns on with A and holds on for the duration after A becomes false.
Inputs (1)
A
Outputs (2)
QET
TYPE: TOFWire in Lab
[TON/TOF]
Timers
On/off-delay
Planned independent delays for switching on and switching off.
Inputs (1)
A
Outputs (2)
QET
TYPE: ON_OFF_DELAYWire in Lab
[TONR]
Timers
Retentive on-delay
Planned timer that retains elapsed time when A is false and clears on R.
Inputs (2)
AR
Outputs (2)
QET
TYPE: RETENTIVE_TONWire in Lab
[TP]
Timers
Wiping relay (pulse output)
Planned pulse lasting up to the configured duration while A is active.
Inputs (1)
A
Outputs (1)
Q
TYPE: PULSE_TIMERWire in Lab
[TP↑]
Timers
Edge triggered wiping relay
Planned timed pulse initiated by a rising input edge.
Inputs (2)
AR
Outputs (1)
Q
TYPE: EDGE_PULSE_TIMERWire in Lab
[CLK]
Timers
Asynchronous pulse generator
Repeats independently configured on and off intervals while the simulation runs.
Inputs (0)
—
Outputs (1)
Q
TYPE: CLOCKWire in Lab
[RND]
Timers
Random generator
Planned seeded random switching delays for repeatable simulations.
Inputs (1)
A
Outputs (1)
Q
TYPE: RANDOMWire in Lab
[STAIR]
Timers
Stairway lighting switch
Planned timed lighting control with a warning interval before switch-off.
Inputs (1)
A
Outputs (1)
Q
TYPE: STAIRWAY_SWITCHWire in Lab
[MULTI]
Timers
Multiple function switch
Planned short-press timed operation and long-press maintained operation.
Inputs (2)
AR
Outputs (1)
Q
TYPE: MULTIFUNCTION_SWITCHWire in Lab
[WEEK]
Timers
Weekly timer
Planned weekday and time schedule using an explicit simulation timezone.
Inputs (0)
—
Outputs (1)
Q
TYPE: WEEKLY_TIMERWire in Lab
[YEAR]
Timers
Yearly timer
Planned recurring calendar date range with explicit timezone handling.
Inputs (0)
—
Outputs (1)
Q
TYPE: YEARLY_TIMERWire in Lab
[SUN]
Timers
Astronomical clock
Planned sunrise and sunset schedule using a location and simulation date.
Inputs (0)
—
Outputs (1)
Q
TYPE: ASTRONOMICAL_CLOCKWire in Lab
[SW]
Timers
Stopwatch
Planned elapsed-time measurement while enabled, cleared by reset.
Inputs (2)
AR
Outputs (1)
ET
TYPE: STOPWATCHWire in Lab
[CTUD]
Counters
Up/down counter
Counts rising CU/CD edges, resets on R, and signals when CV reaches the limit.
Inputs (3)
CUCDR
Outputs (2)
QCV
TYPE: COUNTERWire in Lab
[HOURS]
Counters
Hours counter
Planned operating-time accumulator with reset and a maintenance threshold.
Inputs (2)
AR
Outputs (2)
QCV
TYPE: HOURS_COUNTERWire in Lab
[FREQ]
Counters
Threshold trigger
Planned pulse-frequency measurement and configurable frequency threshold.
Inputs (1)
A
Outputs (2)
QCV
TYPE: FREQUENCY_TRIGGERWire in Lab
[MATH]
Analog processing
Mathematic instruction
Adds, subtracts, multiplies, or divides numeric inputs A and B.
Inputs (2)
AB
Outputs (1)
Q
TYPE: MATHWire in Lab
[CMP]
Analog processing
Analog comparator
Compares two numeric values and returns a digital result.
Inputs (2)
AB
Outputs (1)
Q
TYPE: ANALOG_COMPARATORWire in Lab
[A≥]
Analog processing
Analog threshold trigger
Turns on when the numeric input reaches or exceeds a threshold.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_THRESHOLDWire in Lab
[GAIN]
Analog processing
Analog amplifier
Scales a numeric signal using Q = A × gain + offset.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_AMPLIFIERWire in Lab
[WATCH]
Analog processing
Analog watchdog
Planned deviation monitoring against a captured reference value.
Inputs (2)
AEN
Outputs (1)
Q
TYPE: ANALOG_WATCHDOGWire in Lab
[DIFF]
Analog processing
Analog differential trigger
Planned digital trigger with separate switching thresholds for hysteresis.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_DIFFERENTIALWire in Lab
[MUX]
Analog processing
Analog MUX
Selects numeric input B when S is true; otherwise selects A.
Inputs (3)
ABS
Outputs (1)
Q
TYPE: ANALOG_MUXWire in Lab
[RAMP]
Analog processing
Analog ramp
Planned rate-limited movement toward an input setpoint.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_RAMPWire in Lab
[PI]
Analog processing
PI controller
Planned proportional and integral control with output limits and reset.
Inputs (3)
SPPVR
Outputs (1)
Q
TYPE: PI_CONTROLLERWire in Lab
[PWM]
Analog processing
Pulse width modulation
Planned digital pulse train with numeric duty cycle from 0 to 100 percent.
Inputs (1)
A
Outputs (1)
Q
TYPE: PWMWire in Lab
[FILTER]
Analog processing
Analog filter
Planned time-based smoothing of numeric input samples.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_FILTERWire in Lab
[MIN/MAX]
Analog processing
Maximum/minimum
Planned tracking of observed minimum and maximum values until reset.
Inputs (2)
AR
Outputs (2)
MINMAX
TYPE: MIN_MAXWire in Lab
[AVG]
Analog processing
Average value
Planned moving average across a configurable number of scan samples.
Inputs (1)
A
Outputs (1)
Q
TYPE: AVERAGEWire in Lab
[RS]
Memory & utilities
Latching relay
Stores a digital state. Reset R takes priority when S and R are both true.
Inputs (2)
SR
Outputs (1)
Q
TYPE: RS_LATCHWire in Lab
[TOGGLE]
Memory & utilities
Pulse relay
Toggles its stored state on each rising edge of A.
Inputs (1)
A
Outputs (1)
Q
TYPE: PULSE_RELAYWire in Lab
[MSG]
Memory & utilities
Message texts
Planned enabled text message for a simulated operator display.
Inputs (1)
EN
Outputs (1)
TEXT
TYPE: MESSAGE_TEXTWire in Lab
[SOFT]
Memory & utilities
Softkey
Planned configurable button for an operator panel.
Inputs (0)
—
Outputs (1)
Q
TYPE: SOFTKEYWire in Lab
[SHIFT]
Memory & utilities
Shift register
Planned bit storage shifted on a clock edge, with direction and reset controls.
Inputs (4)
DCLKDIRR
Outputs (1)
Q
TYPE: SHIFT_REGISTERWire in Lab
[ERR]
Memory & utilities
Mathematic instruction error detection
Planned error monitor linked to a calculation block, including divide-by-zero.
Inputs (0)
—
Outputs (1)
Q
TYPE: MATH_ERRORWire in Lab
[INT]
Memory & utilities
Float/integer converter
Truncates the fractional part of a numeric input toward zero.
Inputs (1)
A
Outputs (1)
Q
TYPE: FLOAT_TO_INTWire in Lab
[REAL]
Memory & utilities
Integer/float converter
Passes a numeric input through as a simulation number.
Inputs (1)
A
Outputs (1)
Q
TYPE: INT_TO_FLOATWire in Lab
[↑]
Memory & utilities
Rising edge trigger
Produces one scan of true when A changes from false to true.
Inputs (1)
A
Outputs (1)
Q
TYPE: R_TRIGWire in Lab
[↓]
Memory & utilities
Falling edge trigger
Produces one scan of true when A changes from true to false.
Inputs (1)
A
Outputs (1)
Q
TYPE: F_TRIGWire in Lab
[z⁻¹]
Memory & utilities
One-scan delay
Outputs the previous scan input, providing an explicit memory boundary for feedback.
Inputs (1)
A
Outputs (1)
Q
TYPE: SCAN_DELAYWire in Lab
[z⁻¹]
Analog & math
Analog scan delay
Delays an analog signal by one execution scan to establish an explicit memory boundary for feedback loops.
Inputs (1)
A
Outputs (1)
Q
TYPE: ANALOG_SCAN_DELAYWire in Lab
[LOG]
Data & modules
Data log
Planned timestamped numeric samples with capture controls and CSV export.
Inputs (3)
AENR
Outputs (1)
Q
TYPE: DATA_LOGWire in Lab
[UDF]
Data & modules
User-defined function
Planned reusable circuit module with a declared interface; final pins come from the module definition.
Inputs (0)
—
Outputs (0)
—
TYPE: UDFPlanned Phase 4
[M]
Mechatronics
Servo motor axis
Simulates a closed-loop servo. Moves Current Angle (Q) toward Target Angle (A) at Speed limit.
Inputs (2)
ASPEED
Outputs (1)
Q
TYPE: SERVO_AXISWire in Lab
[DC]
Mechatronics
DC Motor (Physics)
Applies simulated inertia to a voltage input to produce RPM and Position.
Inputs (2)
VLOAD
Outputs (2)
RPMPOS
TYPE: DC_MOTORWire in Lab
[FWD]
Mechatronics
Forward Kinematics 2D
Calculates X/Y tool coordinate from two joint angles.
Inputs (2)
THETA1THETA2
Outputs (2)
XY
TYPE: KINEMATICS_2DWire in Lab
[INV]
Mechatronics
Inverse Kinematics 2D
Calculates required joint angles to reach an X/Y target.
Inputs (2)
XY
Outputs (2)
THETA1THETA2
TYPE: INV_KINEMATICS_2DWire in Lab
[PID]
Mechatronics
PID Controller
Full Proportional-Integral-Derivative control loop.
Inputs (3)
SPPVEN
Outputs (1)
CV
TYPE: PID_CONTROLLERWire in Lab
[TF]
Mechatronics
Transfer Function (1st Order)
Simulates physical lag (inertia, heating). 1 / (Ts + 1)
Inputs (1)
A
Outputs (1)
Q
TYPE: TRANSFER_FUNCTIONWire in Lab
[SIG]
Mechatronics
Signal Generator
Generates continuous test waves (Sine, Square, Triangle).
Inputs (1)
EN
Outputs (1)
Q
TYPE: SIGNAL_GENERATORWire in Lab
[ƒ(x)]
Mechatronics
Math Expression
Evaluates a string math expression (e.g. A * sin(B)).
Inputs (3)
ABC
Outputs (1)
Q
TYPE: MATH_EXPRESSIONWire in Lab
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